Verilog Register Transfer Level Synthesis Essay

1. Field of the Invention

The present invention relates to the field of integrated circuit (IC) design methodology. More particularly, the present invention relates to the field of the IC design process and the conversion process of producing register transfer level definition of ICs from a gate level definition of the ICs.

2. Description of the Related Art

To design and produce an integrated circuit (IC), a specification document is first drafted, and after many intermediate steps, layout level design, performing the functions as defined by the specification, is produced. The layout level design is the lowest level description of the IC design. In the layout level design, the transistors are represented as geometric figures with physical dimensions such as length, width and position.

The IC design process involves complex subprocesses requiring many intermediate steps. At each of these intermediate steps, the IC design is represented at a different level of specificity.

One of the higher level descriptions of an IC design is the Register Transfer Level (RTL) design. In the RTL, variables and data operators represent the IC components such as registers and functional blocks of the sections of the IC. Being a more generic high-level description of the IC, the RTL design could be easily mapped across different IC design process technologies.

The next lower level description of IC in the design process is the Logic Level design at which the IC is defined as a set of interconnecting logic gates such as AND, OR gates and memory components such as flip-flops. This level is also called the Gate Netlist Level, and the IC design at this level of specificity will be referred to as the "Netlist" in this document. Netlist is a more specific definition of the IC design than a RTL design. A Netlist design is much less portable for use in other IC design process technologies because Netlist is technology and process specific. Also, making modifications and upgrading designs in Netlist form is cumbersome. On the other hand, modifying and upgrading RTL designs is relatively easy. Hence, it is desirable to have designs in the RTL form.

The process of translating an RTL design into a Netlist design is commonly referred to as "synthesis." Because the RTL methodology of expressing designs is a relatively new concept, most earlier IC designs were hand-tuned or hand-crafted at the Netlist level without having a corresponding RTL designs. In fact, many of the current IC designs exist only as Netlist definitions. Since tremendous effort has gone into these designs and many of these designs have to be used in newer process technologies, obtaining a RTL description of these designs would prove to be very useful.

As the IC design process technology developed over the years and the IC designs became increasingly larger and more complex, the industry developed many different process technologies to implement IC designs. Most of these process technologies support synthesis of RTL designs into their corresponding Netlist designs and, eventually, Layout Level designs. However, the IC designs existing only at the Netlist level cannot take advantage of the new process technologies because Netlists are highly process and technology dependent. Once a design is mapped to a one process technology it is very difficult to migrate to another process technology. For example, at the layout level a NAND gate in one process technology would inherit different electrical characteristics such as capacitance, and rise time, etc. But when migrating to another technology the NAND gates available in the new technology would not essentially have the same electrical characteristics as the previous one.

The present invention discloses a method to overcome this problem by converting, or reverse-synthesizing, Netlist designs into corresponding RTL designs defining the same IC. After reverse-synthesizing Gate Netlist definitions into corresponding RTL designs, the IC design which was defined using only the Netlist definition can now be ported to other, new process technologies.

A company called Chrysalys offers a reverse-synthesis tool to convert Netlist designs to behavioral level designs which are similar to RTL designs. However, Chrysalys' reverse-synthesis is performed using a mathematical equivalence method and the resultant behavioral level designs are generally not synthesizable using new IC design process technologies.

The only other remaining option for reverse-synthesizing Netlist designs into RTL designs is to manually study the Netlist to hand-generate the corresponding RTL design. However, this is very time consuming, lacks a refined methodology, and is prone to error.

The present invention provides a system for generating a RTL definition for an integrated circuit (IC) design by analyzing the Netlist definition of the IC. According to a broad aspect of the present invention, the conversion from a Netlist design to an RTL design is accomplished by parsing and analyzing the Netlist design and generating the corresponding RTL design using the information. Then, the RTL design is verified by running a predetermined set of inputs, or verification suites, on the Netlist and on the RTL designs, and comparing the results.

To parse and analyze the Netlist, identifiable patterns of memory components in the Netlist are located and correlated with matching RTL definitions from a predefined RTL library. Then, the combinational logic between the identified patterns of the Netlist is analyzed. Finally, a corresponding RTL definition is generated using the matched RTL definitions and the combinational logic connections between the identified patterns.

The verification of the RTL design is done by running verification suites against the Netlist design, running the same suite against the RTL design, and comparing the results.

The present invention may be implemented as a computer program executable by specialized or a general purpose computer, or a specially designed apparatus to process Netlist definitions to produce RTL designs.

FIG. 1 is a flowchart illustrating the steps taken to reverse-synthesize Netlist designs to corresponding register transfer level (RTL) design and to verify the new design;

FIG. 2 is a flowchart illustrating the Netlist parsing and analysis process in a greater detail;

FIG. 3 is a sample integrated circuit (IC) design which may be represented by a Netlist design;

FIG. 4 is a sample hash table and the associated linked list produced from the Netlist analysis process;

FIG. 5A is a flowchart illustrating the verification process in a greater detail;

FIG. 5B is an example of a Integrated Circuit design as defined by a Netlist definition and as defined by an RTL definition;

FIG. 6 is a block diagram of an exemplary embodiment of a system for performing the Netlist to RTL conversion process; and

FIG. 7 is a block diagram of an exemplary embodiment of a computer system implemented in accordance with the principles of the present invention.

Referring to the drawings, particularly to FIG. 1, a process to reverse-synthesize a gate Netlist level design (the "Netlist") defining an integrated circuit (IC) into a register transfer level design (the "RTL design") defining the same IC, and to verify the fact that the generated RTL design performs the same functions as the gate netlist design, is illustrated.

First, the Netlist is parsed and analyzed, as represented by block 10. The parse and analysis step may involve identifying or comparing various parts of the Netlist to predefined RTL constructs. The information obtained during the parsing and analyzing of the Netlist may be saved as a table, a list, or another data structure.

Utilizing the information gained from parsing and analyzing the Netlist, a corresponding RTL design is generated for the IC defined by the Netlist, as represented by block 12. After generating the RTL design, the RTL design is verified to confirm that the IC design as represented by the RTL design behaves like the IC design represented by the Netlist, as represented by block 14.

Referring now to FIG. 2, a flowchart illustrating the Netlist parse and analysis process is presented in a greater detail. First, the Netlist is searched 20 for predetermined identifiable memory component patterns. The identifiable patterns may be predetermined and coded into a search program or may be defined by another input file or a library listing all the Netlist patterns to be identified. Typically, Netlist definitions describing flip-flops are identified because flip-flops are generally used for registers of an IC.

When a pattern is identified 22, the identified pattern is correlated to an RTL construct of an RTL library 24. Then, each input and output connections of the identified pattern is traced to its termination point which is a primary input, a primary output, or an input or an output of another identified pattern 26. While tracing the inputs and the outputs of the identified pattern, the information relating to the combination logic gates in between the identified pattern and the termination points of the input and the output connections is saved. This process continues until the end of the Netlist is reached 28.

After the entire Netlist has thus been searched and analyzed, an RTL design, describing the same IC as the Netlist, is generated. The RTL design is generated by utilizing the RTL constructs, which the identified patterns in the Netlist correlate to, and by expressing, in the language used to define the RTL design, the combinational logic connections. Typically a high level definition language (HDL) such as Verilog is used to define an RTL design.

A sample integrated circuit (IC) design which may be represented by a Netlist design is illustrated by FIG. 3. FIG. 4 illustrates a hash table and associated linked-lists, which, collectively represent the information gathered from parsing and analyzing of the Netlist. Alternative embodiments of the present invention may use other data structures to represent the information gathered from parsing and analyzing the Netlist. In the preferred embodiment as disclosed by FIG. 4, a hash table is used to maintain the list of identified patterns for efficient access.

Referring to FIGS. 3 and 4, one implementation of the parse and the analysis process of a Netlist of the present invention may be discussed in detail. In the example illustrated by the figures, elements 60 and 70 may be the identifiable memory component patterns of the Netlist. In one embodiment of the present invention, the reverse-synthesis process identifies flip-flops of the Netlist and correlates them to matching RTL constructs of an RTL library. Here, the flip-flops 60 and 70 are identified and a hash table 50 is updated to include the Netlist name for the flip-flops 60' and 70' and their correlated RTL construct names 60" and 70". The hash table is caused to point to linked-lists which contain information regarding the input and output connections of each of the identified patterns.

Each input and output connections for each of the identified patterns 60 and 70 is traced to its termination point, which may be a primary input, a primary output, or another identified pattern. In addition, for each of the inputs and outputs traced, an element is created in the linked-list, associated with the corresponding flip-flop in the hash table, describing the links of the connections to a termination point, including any combinational logic which may couple the connection to a termination point. In the example, for the flip-flop 60, the input connections 61 and 62 are traced and the output connection 63 is traced. For the connections 61, 62, and 63, elements 61', 62', and 63' in the linked-list 69, pointed to by the hash table entry for the pattern 60, are created. As FIG. 3 illustrates, the connection 61 is traced to the primary inputs A, B, and C, and the element 61' contains the primary inputs as well as the combinational logic between the primary inputs and the connection 61, namely an NAND gate 65 and an OR gate 64. The connection 62 is traced to the system clock and this is noted by the element 62'. The output connection 63 is traced to the primary output f1 and to the primary output f2 and the second flip-flop 70 via an AND gate 66 and an INVERTER 67. The element 63' contains the information relating to the output connection 63.

Likewise, the connections 71, 72, and 73 for the flip-flop 70 are traced to their termination points and the linked-list elements 71', 72', and 73' are caused to contain the connection information and combinational logic information for the connections 71, 72, and 73, respectively.

Following the parse and the analysis of the Netlist, the resulting hash table 50 and the associated linked-lists 69 and 79 are used to create an RTL design of the IC. More specifically, an RTL design is generated using the RTL names for the Netlist modules which were identified as having an equivalent RTL constructs, and expressing the connections and the combinational logic of the connections, as defined by the linked-lists, using RTL expressions. Utilizing the example circuit of FIG. 3, a sample RTL design generated may appear as follows:

______________________________________Always at (posedge clock)Begin s1 < = #T.P. ( not(A and B) or C);EndAlways at (posedge clock)Begin f3 < = #T.P. (not (s1 and D));EndAssign f1 = s1Assign f2 = not (s1 and D)______________________________________

Thus the RTL design is created from the information gathered from the analysis of the Netlist design.

If the netlist exists in a form such that it is hierarchically divided into modules, the corresponding RTL will represent the same hierarchy. However, if the netlist is not divided into modules and is a flat representation of the design, the corresponding RTL will also be a flat representation of the design.

Once the RTL has been generated, it is necessary to verify the validity of the RTL representation against the original Netlist design. All existing designs are verified for correctness of functionality and it is safe to assume that a verification suite already exists for the Netlist design. The verification methodology described in this patent uses the same verification suite to verify the correctness of the RTL representation.

Verification can be done at either the top level of the design, or hierarchically at the module level. The methodology described below is applicable to either approach. It is assumed that the verification suite exists for the top level design and is in a form that specifies the input stimuli and the corresponding output response. This is the minimum form in which a verification suite can exist. If verification is available at module level, for a hierarchical design, the same methodology applies.

Referring to FIG. 5A, a flowchart illustrating the verification process is presented in a greater detail. In describing the verification process, a sample IC designs as illustrated by FIG. 5B is used. FIG. 5B shows the sample IC design as defined by a Netlist and as defined by an RTL definition. The following discussion will refer to FIGS. 5A and 5B.

Each of the submodules of the IC as defined by the RTL is tested following the steps discussed below.

First, an RTL module is selected to be tested as indicated by the reference number 80. This module is called a Module Under Test (MUT). For example, FIG. 5B illustrates a sample IC design as defined by the Netlist (the "Netlist circuit") 91 and the same IC design as defined by the new RTL definition (the "RTL circuit") 91'. Each of the modules of the RTL circuit 91', mod 90' and Mod 92' will be selected, in turn, to be verified. Finally, the top level RTL circuit 91' will be verified. In the following discussions, we will assume that RTL module Mod 92' is selected as the MUT.

Second, a test bench is automatically generated for the selected module as indicated by reference number 81. A test bench is a setup which enables one to apply input stimuli to the module under test (MUT) and monitor the outputs of the MUT. A test bench can be completely defined by the MUT, the input signals and the output signals. For example, (S', D') are inputs of the Module 92' and (F') is the output of the Module 92', where, S' is the output signal of the Module 90' and D' is one of the primary inputs to the IC design illustrated by FIG. 5B. A test bench can apply prespecified stimuli (called input vector) to the inputs (S', D') and monitor the output F' to capture the response of the MUT to the input stimuli. We will call the input vectors and the corresponding output responses, signal vectors for the test bench.

After the test bench for the selected module is generated, the signal vectors for the test bench are extracted by (1) identifying the corresponding module in the Netlist circuit 91, as indicated by the reference number 82, and (2) applying a predetermined set of inputs from the existing verification suite to the primary inputs of the Netlist circuit 91, and (3) scoping, or reading the input signals of the identified module to form the input vectors for the selected module. (4) The output signals of the identified module are also scoped or read, to capture the expected response, as indicated by reference number 85.

The identification of the selected module from RTL, in the Netlist description, is also an automated process, and can be easily accomplished with the aide of the input and output signals of the module. The signal vectors for testing of a module can be extracted as described above, for the entire verification suite or a part of it, as deemed necessary. These extracted signal vectors are then used for the verification of the MUT.

For example, the IC Netlist design of FIG. 5B includes four primary input lines (A, B, C, and D), one intermediate signal line (S), and one output lines (F). After identifying the module Mod 92 as the corresponding Netlist module to the RTL Mod 92' to be verified, a predetermined set of signal vectors from the verification suite are applied to the primary input lines A, B, C, and D. The predetermined set of signal vectors may comprise {0, 0, 0, 0}, {0, 0, 0, 1}, {0, 0, 1, 0}, . . . {1, 1, 1, 1}.

While the predetermined set is being applied to the primary input lines, the values for the input lines (input vectors) for Mod 92, D and S, are scoped, and the value for the output line F is scoped as indicated by the reference numbers 83 and 85. In this example, the lines D and S, inputs for the MUT, are scoped as well as the line F.

Third, the input vectors scoped from the lines D and S of the Netlist circuit 91 are applied to the lines D' and S', the input lines for the RTL Mod 92' through the test bench, and the output F' is scoped, as indicated by the reference number 84.

Finally, the scoped output F of the Netlist circuit 91 is compared with the scoped output F' of the RTL circuit 91', and a verification report is generated. If the outputs match, then the RTL Module Under Test (MUT) is assumed to be coded correctly in the RTL and can be synthesized by setting the appropriate load and timing requirements for the input and the output signals. However, if there are mismatches between the outputs of the RTL MUT signals and the Netlist MUT signals, then the tool generates a report containing the signal names that are mismatching, their values, and the timing of the mismatches. The report is used to troubleshoot the generated RTL definition or the RTL generation parameters and the process.

Not only is the above methodology applicable to submodules, it is also applicable to the top level design by simply considering the top level design as a module.

Referring now to FIG. 6, an exemplary embodiment of a hardware system implemented in accordance with the methodology and the principles of the present invention is shown. Data 100, representing a Netlist is input into a Netlist Parser 102 as well as to a Netlist and RTL Verifier 110. The Parser 102 parses and analyzes the Netlist to generate hash tables and linked-lists and forwards 104 them to the RTL Generator 106. The RTL Generator 106 generates the corresponding RTL design from the hash tables and the linked-lists, and passes the RTL design 108 to the Netlist and RTL Verifier 110.

The Netlist data 100 and the RTL design 108 is received by the Verifier 110 which runs a predetermined sets of test suites against various components of the Netlist and the RTL design, compares the test results, and produces a test comparison report 112.

Referring to FIG. 7, an exemplary embodiment of a computer system implemented in accordance with the principles of the present invention is shown. The computer system includes a communication system bus 134 to which a central processing unit (CPU) 124 and a memory 128 are coupled. An input device 122 and an output device 126 are also coupled to the system bus 134.

The input device 122 may be any type of input device such as a keyboard, a monitor, a port, a memory system such as a ROM, RAM, or a computer readable disk and driver, or another computing unit attached to the system to provide the computing system 120 with the Netlist data 100' to be reverse-synthesized. The output device 126 may be any type of output device such as a port, a monitor, a printer, or other electronic memory systems.

The memory 128 may comprise RAM, ROM, magnetic, optical, or other electronic or mechanical memory device which can store the instructions and data for the CPU 124 to perform the Netlist to RTL design reverse-synthesis functions in accordance with the present invention. In particular, the memory 128 may comprise a set of instructions 130 to perform the functions of the Parser, the Generator, and the Verifier as discussed above. In addition, the memory 128 comprise other data 132 to aid in the performance of the steps of the present invention such as a Library of RTL Constructs and one or more Test Suites to be used to verify RTL designs.

The system 120 operates when the CPU 124 executes the programming steps as defined by the Parser, the Generator, and the Verifier 130 and reads the Netlist data 100' using the input device 122 and performs the functions the steps discussed above to analyze the Netlist, generate an RTL design, and verifies the RTL design. Finally, the CPU 124 causes the output device 126 to produce the resultant RTL design and the verification report 112'.

Thus disclosed are methods and apparatus for reverse-synthesizing a gate level definition of an integrated circuit design into a register transfer level definition of the integrated circuit.

Although the present invention has been described in detail with regard to the exemplary embodiments and drawings thereof, it should be apparent to those skilled in the art that various adaptations and modifications of the present invention may be accomplished without departing from the spirit and the scope of the invention. Therefore, the present invention is not limited to the precise embodiments described hereinabove.

Not to be confused with Register transfer language.

In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronousdigital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals.

Register-transfer-level abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived. Design at the RTL level is typical practice in modern digital design.[1]

RTL description[edit]

A synchronous circuit consists of two kinds of elements: registers (Sequential logic) and combinational logic. Registers (usually implemented as D flip-flops) synchronize the circuit's operation to the edges of the clock signal, and are the only elements in the circuit that have memory properties. Combinational logic performs all the logical functions in the circuit and it typically consists of logic gates.

For example, a very simple synchronous circuit is shown in the figure. The inverter is connected from the output, Q, of a register to the register's input, D, to create a circuit that changes its state on each rising edge of the clock, clk. In this circuit, the combinational logic consists of the inverter.

When designing digital integrated circuits with a hardware description language, the designs are usually engineered at a higher level of abstraction than transistor level (logic families) or logic gate level. In HDLs the designer declares the registers (which roughly correspond to variables in computer programming languages), and describes the combinational logic by using constructs that are familiar from programming languages such as if-then-else and arithmetic operations. This level is called register-transfer level. The term refers to the fact that RTL focuses on describing the flow of signals between registers.

As an example, the circuit mentioned above can be described in VHDL as follows:

D<=notQ;process(clk)beginifrising_edge(clk)thenQ<=D;endif;endprocess;

Using an EDA tool for synthesis, this description can usually be directly translated to an equivalent hardware implementation file for an ASIC or an FPGA. The synthesis tool also performs logic optimization.

At the register-transfer level, some types of circuits can be recognized. If there is a cyclic path of logic from a register's output to its input (or from a set of registers outputs to its inputs), the circuit is called a state machine or can be said to be sequential logic. If there are logic paths from a register to another without a cycle, it is called a pipeline.

RTL in the circuit design cycle[edit]

RTL is used in the logic design phase of the integrated circuit design cycle.

An RTL description is usually converted to a gate-level description of the circuit by a logic synthesistool. The synthesis results are then used by placement and routing tools to create a physical layout.

Logic simulation tools may use a design's RTL description to verify its correctness.

Power estimation techniques for RTL[edit]

The most accurate power analysis tools are available for the circuit level but unfortunately, even with switch- rather than device-level modelling, tools at the circuit level have disadvantages like they are either too slow or require too much memory thus inhibiting large chip handling. The majority of these are simulators like SPICE and have been used by the designers for many years as performance analysis tools. Due to these disadvantages, gate-level power estimation tools have begun to gain some acceptance where faster, probabilistic techniques have begun to gain a foothold. But it also has its trade off as speedup is achieved on the cost of accuracy, especially in the presence of correlated signals. Over the years it has been realized that biggest wins in low power design cannot come from circuit- and gate-level optimizations whereas architecture, system, and algorithm optimizations tend to have the largest impact on power consumption. Therefore, there has been a shift in the incline of the tool developers towards high-level analysis and optimization tools for power.

Motivation[edit]

It is well known that more significant power reductions are possible if optimizations on higher levels of abstraction are made like the architectural and algorithmic level than at the circuit or gate level.[2] This provides the required motivation for the developers to focus on the development of new architectural level power analysis tools. This in no way imply that lower level tools are unimportant. Instead, each layer of tools provides a foundation upon which the next level can be built. The abstractions of the estimation techniques at a lower level can be used to higher level and applied again with slight modifications.

Advantages of doing power estimation at RTL or architectural level[edit]

  • The Register-transfer level(RTL) input description of the design allows the designer to make optimizations and trade-offs very early in the design flow.
  • The presence of functional blocks in an RTL description makes the complexity of the architectural design much more manageable even for large chips due to its large enough granularity than the corresponding gate- or circuit-level descriptions.

Gate Equivalents[3][edit]

It is a technique based on the concept of gate equivalents. The complexity of a chip architecture can be described approximately in terms of gate equivalents where gate equivalent count specifies the average number of reference gates that are required to implement the particular function.The total power required for the particular function is estimated by multiplying the approximated number of gate equivalents with the average power consumed per gate. The reference gate can be any gate e.g. 2-input NAND gate.

Examples of Gate Equivalent technique[edit]

  • Class-Independent Power Modeling: It is a technique which tries to estimate chip area, speed, and power dissipation based on information about the complexity of the design in terms of gate equivalents. The functionality is divided among different blocks but no distinction is made about the functionality of the blocks i.e. it is basically class independent. This is the technique used by the Chip Estimation System (CES).
Steps:
  1. Identify the functional blocks such as counters, decoders, multipliers, memories, etc.
  2. Assign a complexity in terms of Gate Equivalents. The number of GE’s for each unit type are either taken directly as an input from the user or are fed from a library.

P = ∑i∈{fns} GEi (Etyp + CLi Vdd2) f Ainti

Where Etyp is the assumed average dissipated energy by a gate equivalent,when active. The activity factor, Aint, denotes the average percentage of gates switching per clock cycle and is allowed to vary from function to function. The capacitive load, CL, is a combination of fan-out loading as well as wiring. An estimate of the average wire length can be used to calculate the wiring capacitance. This is provided by the user and cross-checked by using a derivative of Rent’s Rule.
Assumptions:
  1. A single reference gate is taken as the basis for all the power estimates not taking into consideration different circuit styles, clocking strategies, or layout techniques.
  2. The percentage of gates switching per clock cycle denoted by Activity factors are assumed to be fixed regardless of the input patterns.
  3. Typical gate switching energy is characterized by completely random uniform white noise (UWN) distribution of the input data. This implies that the power estimation is same regardless of the circuit being idle or at maximum load as this UWN model ignores how different input distributions affect the power consumption of gates and modules.[4]
  • Class-Dependent Power Modeling: This approach is slightly better than the previous approach as it takes into account customized estimation techniques to the different types of functional blocks thus trying to increase the modelling accuracy which wasn’t the case in the previous technique such as logic, memory, interconnect, and clock hence the name. The power estimation is done in a very similar manner to the independent case. The basic switching energy is based on a three-input AND gate and is calculated from technology parameters e.g. gate width, tox, and metal width provided by the user.

Pbitlines = Ncol / 2 * (Lcol Cwire + Nrow Ccell) Vdd Vswing

Where Cwire denotes the bit line wiring capacitance per unit length and Ccell denotes the loading due to a single cell hanging off the bit line. The clock capacitance is based on the assumption of an H-tree distribution network. Activity is modelled using a UWN model.As can be seen by the equation the power consumption of each components is related to the number of columns (Ncol) and rows (Nrow) in the memory array.
Disadvantages:
  1. The circuit activities are not modeled accurately as an overall activity factor is assumed for the entire chip which is also not trustable as provided by the user. As a matter of fact activity factors will vary throughout the chip hence this is not very accurate and prone to error. This leads to the problem that even if the model gives a correct estimate for the total power consumption by the chip, the module wise power distribution is fairly inaccurate.
  2. The chosen activity factor gives the correct total power, but the breakdown of power into logic, clock, memory, etc. is less accurate. Therefore this tool is not much different or improved in comparison with CES.

Precharacterized Cell Libraries[edit]

This technique further customizes the power estimation of various functional blocks by having separate power model for logic, memory, and interconnect suggesting a Power Factor Approximation (PFA) method for individually characterizing an entire library of functional blocks such as multipliers, adders, etc. instead of a single gate-equivalent model for “logic” blocks.
The power over the entire chip is approximated by the expression:

P = ∑ i∈{all blocks} Ki G i f i

Where Ki is PFA proportionality constant that characterizes the ith functional element,Gi is the measure of hardware complexity, and fi denotes the activation frequency.

Example[edit]

Gi denoting the hardware complexity of the multiplier is related to the square of the input word length i.e. N2 where N is the word length.The activation frequency is the rate at which multiplies are performed by the algorithm denoted by fmult and the PFA constant, Kmult, is extracted empirically from past multiplier designs and shown to be about 15 fW/bit2-Hz for a 1.2 µm technology at 5V. The resulting power model for the multiplier on the basis of the above assumptions is:

Pmult = Kmult N 2 f mult

Advantages:

  • Customization is possible in terms of whatever complexity parameters which are appropriate for that block. E.g. for a multiplier the square of the word length was appropriate. For memory, the storage capacity in bits is used and for the I/O drivers the word length alone is adequate.

Weakness:

  • There is the implicit assumption that the inputs do not affect the multiplier activity which is contradictory to the fact that the PFA constant Kmult is intended to capture the intrinsic internal activity associated with the multiply operation as it is taken to be a constant.

The estimation error (relative to switch-level simulation) for a 16x16 multiplier is experimented and it is observed that when the dynamic range of the inputs doesn’t fully occupy the word length of the multiplier, the UWN model becomes extremely inaccurate.[5] Granted, good designers attempt to maximize word length utilization. Still, errors in the range of 50-100% are not uncommon. The figure clearly suggests a flaw in the UWN model.

See also[edit]

Power estimation[edit]

References[edit]

Example of a simple circuit with the output toggling at each rising edge of the input. The inverter forms the combinational logic in this circuit, and the register holds the state.

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